In JP-2001-251171, a delay circuit is disclosed which uses a capacitor with an MOS (Metal-Oxide-Semiconductor) structure (hereinafter referred to as an MOS capacitor) of a p-channel type and an MOS capacitor of an n-channel type as delay elements.
As it will be explained later, an MOS capacitor has a characteristic of varying the capacitance thereof with a gate voltage (voltage dependence). Thus, when such an MOS capacitor is used as a delay element of a delay circuit, the influence on a delay time due to the voltage dependence of the MOS capacitor must be reduced.
Hence, in the delay circuit according to JP-2001-251171, a specified voltage beyond the range of a power supply voltage is provided so as to be applied to the substrate (back gate) of each of the MOS capacitors. Namely, the delay circuit is provided so that, with respect to the MOS capacitor formed of a p-channel MOSFET, a specified voltage higher than the power supply voltage is applied to the substrate, and with respect to the MOS capacitor formed of an n-channel MOSFET, a specified voltage lower than the grounding voltage (0V) is applied to the substrate. The value of each of the voltages applied to the substrate is set at a value at which the MOS capacitor exhibits a constant capacitance value whenever a voltage of any magnitude within the power supply voltage is applied to the gate of the MOS capacitor.